[1]
V. C, M. R. Y, R. S, and S. K. T, “Performance Analysis of Nano Transistor Based Binary and Ternary Logic Gates”, IJIE, vol. 16, no. 2, pp. 66–75, Apr. 2024, Accessed: Nov. 07, 2026. [Online]. Available: https://journal.uthm.edu.my/index.php/ijie/article/view/14671