Performance Evaluation of RISC-V Microcontroller System on FPGA: A Study of the NEORV32 Core - Wei Peng , Chung; Jambek , Asral Bahari; Baskara Dass, Sreedharan; Lim , Teik Wah; L. Laudis, Lalin; Yadlapati, Avinash; Udari, Gnaneshwara Chary; B. Rama , Sanjeeva Reddy (International Journal of Integrated Engineering, 2024)
This paper evaluates a RISC-V microcontroller system on an FPGA platform using the NEORV32 core. This research aims to identify performance gaps in the NEORV32 system on an FPGA. The evaluation was carried out using the CoreMark benchmark programs. The hardware utilisation of the NEORV32 core is examined using Quartus Prime software with a particular focus on slice look-up tables (LUTs), total registers, memory bits, RAM blocks, and DSP blocks. In this work, two NEORV32 implementations are evaluated, which are RV32I and RV32I with M and Zfinx extension (RV32I_MC_zfinx). The effect of dedicated hardware and special operations on the performance of the processors is also evaluated on an FPGA board. The experiment results show that RV32I_MC_zfinx consumes 55% and 65% more LUT and registers resources, respectively, compared to the RV32I. Implementing hardware accelerators to RV32I_MC_zfinx results in a 48% increase in CoreMark score. Compared with other existing RISC-V cores, NEORV32 is a good option for embedded system development since it balances performance and resource efficiency for low-power applications.